1. Field of the Invention
The present invention relates generally to the field of testing memory circuits on integrated circuits, both stand-alone and embedded. More particularly, the present invention relates to a pad efficient and speed efficient method and apparatus for testing for column leakage characteristics in semiconductor memory devices.
2. Description of the Prior Art
From a practical standpoint, there are two conditions which must be satisfied in order for VLSI circuit fabrication to continue to be a useful, burgeoning technology. First, the fabricated circuits must be capable of being produced in large quantities at costs which are competitive with alternative methods of achieving the same circuit and system functionality. Second, the circuits must be capable of performing their functions throughout their intended useful life.
In order to deal successfully with these two requirements, various methods have been developed to identify the diverse mechanisms which seriously limit the yield and reliability of VLSI circuits. Likewise, prodigious attempts have been made at developing accurate yield and reliability modeling parameters to enable the manufacturer of VLSI circuits to better predict the reliability of products. Economically, it is very critical for the circuit fabricator to be able to detect those integrated circuits of a certain class which are unreliable due to a particular type of reliability failure mechanism.
Ideally, in a properly fabricated wafer of integrated circuits, one would expect all of the circuits to be good functional devices. However, in practice, the number of good circuits per wafer may range anywhere from 0 to 100%, depending on the process employed and the relative complexity of the circuit. The causes for less than perfect yield often depend on the category or class of integrated circuits which are being fabricated. For instance, low yield and reliability may be due to systemic processing problems, circuit design problems or random point defects in the circuit.
One class of integrated circuits contain floating-gate memory devices which utilize hot electron injection to add electrons to, and "FOWLER-NORDHEIM" tunneling to remove electrons from floating gates. Such ICs are often called EEPROMs, E.sup.2 PROMSs, flash EPROMs, or non-volatile memories. It must be noted that not all flash memories employ the electron tunneling mechanism and that each non-volatile class has its own unique characteristics. Floating gate cells which rely on tunnelling may also be used in other types of integrated circuits as well.
One type of failure that has plagued memory devices in the past is excessive column leakage, hereinafter referred to as leaky columns. Leaky columns can be caused by a number of failure mechanisms, including the following: 1) resistive shorts from the column metal to the wordline, adjacent columns or ground straps; 2) negative electrical erase thresholds due to overerase; 3) spiked column drain contacts; and 4) defects in the bulk silicon shorting either the source to the drain or the source or drain to the substrate. Several of these defects are latent, can degrade over time, or through later processing. Flash memories have suffered from dual column shorts during cycling while-EPROMs have seen speed shifting in burn-in due to junction spiking.
As is appreciated by the practitioners in the art, column leakage characteristics can dramatically affect correct data output in memory devices and/or access speed degradation. Non-volatile memories should be able to withstand numerous program/erase cycles of the integrated circuit. The ability of a silicon memory device to survive such cycling is called the chip's "reliability" or "endurance". An IC failing after a given cycling operation is frequently referred to as suffering "endurance failure".
Note the term "reliability" as used in this context, refers to the probability that an IC will perform a required function for a stated period of time. For floating gate memory device, the "required function" is generally defined as its ability to cycle a given number of times. For example, properly fabricated EEPROMs and flash EPROMs are generally expected to cycle anywhere between 10,000 and 100,000 times before experiencing endurance failure.
For memory circuits it is therefore desirable to screen for columns that show any charge leakage characteristics. In some memory technologies, single column measurements must be made with nano-amp accuracies. Locating a single defective column out of the several thousand that may make up the total memory array can take many seconds of test system time. Test system time on modern VLSI testers represents an increasing fraction of the total cost of a product.
The standard method for testing for columns that show leakage characteristics is to use the chip tester's Precision Measurement Unit (PMU). First, the PMU is usually initialized to zero volts to avoid `hot switching` the pins that will later be attached to the unit. The second step is then to select a pin or group of pins to be switched from their channel driver circuits onto the PMU circuit; the tester controls this switching under tester program commands. The PMU is then set to the forcing voltage and after some delay, a measurement is made. Subsequent tests usually require a reverse of the set-up process; the PMU is forced back to the `safe` state and the pins disconnected, then new pins are connected and the PMU forced back to the measurement voltage. This PMU manipulation and pin selection make up the bulk of the tester time to actually execute the desired test.
There is also a limitation for adding and subtracting pins to the PMU due to the AC loading effects of the device under test. Some test heads have very large capacitances associated with each pin. Pin capacitance of over 100 pF are not unusual. Switching large capacitances requires time for settling and setup, thus increasing the total time needed to complete stable low current noise-free measurements. The switching mechanism for bit plane output pins, to the tester channels, are electro-mechanical relays.
Each bit plane has its digital data output as well as an analog output line. For testing, a test voltage is applied across the rows of the memory array. Current measurements of either the whole bit plane's analog output or individual columns are then measured to detect column leakage. The analog output current must be precisely measured to accurately determine column leakage characteristics. Too much measured current indicates a leaky column and likely a bit plane or device that will not live up to its endurance requirements.
In order to test for column leakage, it is necessary to apply a predetermined test voltage across the word lines of the memory array. U.S. Pat. Nos. 4,841,482 and 4,860,261, assigned to the assignee of the present invention, disclose circuitry and a method for accomplishing this necessary task in the case of flash EPROMS. Those patents are incorporated herein by reference. Another U.S. Pat. No. 4,963,825, assigned to the assignee of the present invention discloses a method of testing cells in a flash memory array for charge leakage from the floating gates of the transistors that make up the memory cells.